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MCP4821/MCP4822
12-Bit DACs with Internal VREF and SPITM Interface
Features
* * * * * * * * * * * * * 12-Bit Resolution 0.2 LSb DNL (typ.) 2 LSb INL (typ.) Single or Dual Channel Rail-to-Rail Output SPITM Interface with 20 MHz Clock Support Simultaneous Latching of the Dual DACs with LDAC pin Fast Settling Time of 4.5 s Selectable Unity or 2x Gain Output 2.048V Internal Band Gap Voltage Reference 50 ppm/C VREF Temperature Coefficient 2.7V to 5.5V Single-Supply Operation Extended Temperature Range: -40C to +125C
Description
The Microchip Technology Inc. MCP482X devices are 2.7V-5.5V, low-power, low DNL, 12-bit Digital-to-Analog Converters (DACs) with internal band gap voltage reference, optional 2x-buffered output and Serial Peripheral Interface (SPITM). The MCP482X family of DACs provide high accuracy and low noise performance for industrial applications where calibration or compensation of signals (such as temperature, pressure and humidity) are required. The MCP482X devices are available in the extended temperature range and PDIP, SOIC and MSOP packages. The MCP482X devices utilize a resistive string architecture, with its inherent advantages of low DNL error, low ratio metric temperature coefficient and fast settling time. These devices are specified over the extended temperature range. The MCP482X family includes double-buffered registers, allowing simultaneous updates using the LDAC pin. These devices also incorporate a Power-On Reset (POR) circuit to ensure reliable power-up.
Applications
* * * * * Set Point or Offset Trimming Sensor Calibration Precision Selectable Voltage Reference Portable Instrumentation (Battery-Powered) Calibration of Optical Communication Devices
Package Types
8-Pin PDIP, SOIC, MSOP
CS 2 SCK 3 SDI 4
MCP4821 MCP4822
Block Diagram
CS SDI SCK LDAC
VDD 1
8 VOUTA 7 AVSS 6 SHDN 5 LDAC
Interface Logic
Power-on Reset
VDD
AVSS Input Register A DACA Register Input Register B DACB Register String DACB 2.048V VREF
8-Pin PDIP, SOIC, MSOP
VDD 1 CS 2 SCK 3 SDI 4 8 VOUTA 7 AVSS 6 VOUTB 5 LDAC
String DACA
Gain Logic
Output Op Amps Output Logic
Gain Logic
VOUTA
SHDN
VOUTB
(c) 2005 Microchip Technology Inc.
DS21953A-page 1
MCP4821/MCP4822
1.0 ELECTRICAL CHARACTERISTICS
Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
VDD ............................................................................................................. 6.5V All inputs and outputs ...................AVSS - 0.3V to VDD + 0.3V Current at Input Pins ....................................................2 mA Current at Supply Pins ...............................................50 mA Current at Output Pins ...............................................25 mA Storage temperature .....................................-65C to +150C Ambient temp. with power applied ................-55C to +125C ESD protection on all pins ........... 4 kV (HBM), 400V (MM) Maximum Junction Temperature (TJ) . .........................+150C
5V AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x, RL = 5 k to GND, CL = 100 pF, TA = -40 to +85C. Typical values at +25C. Parameters Power Requirements Input Voltage Input Current - MCP4821 Input Current - MCP4822 Hardware Shutdown Current Software Shutdown Current Power-on-Reset Threshold DC Accuracy Resolution INL Error DNL (Note 1) Offset Error Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Nominal Reference Voltage Temperature Coefficient (Note 1) n INL DNL VOS VOS/C gE 12 -12 -0.75 -1 -- -- -2 -- -- 2 0.2 0.02 0.16 -0.44 -0.10 -3 -- 12 +0.75 1 -- -- 2 -- Bits LSb LSb % of FSR ppm/C ppm/C % of FSR ppm/C Device is monotonic Code = 0x000h -45C to 25C +25C to 85C Code 0xFFFh, not including offset error VDD IDD ISHDN ISHDN_SW VPOR 2.7 -- -- -- -- -- -- 330 415 0.3 3.3 2.0 5.5 400 750 2 6 -- A A A V Digital inputs grounded, Output unloaded, code = 0x000 Sym Min Typ Max Units Conditions
G/C
VREF
Internal Voltage Reference (VREF) 2.008 -- -- -- -- Output Noise (VREF Noise) Output Noise Density ENREF (0.1-10 Hz) eNREF (1 kHz) eNREF (10 kHz) 1/f Corner Frequency Note 1: 2: fCORNER By design, not production tested. Too small to quantify. -- -- -- -- 2.048 125 0.25 45 0.09 290 1.2 1.0 400 2.088 325 0.65 160 0.32 -- -- -- -- V ppm/C LSb/C ppm/C LSb/C Vp-p V/Hz V/Hz Hz VOUTA when G = 1x and Code = 0xFFFh -40C to 0C -40C to 0C 0C to +85C 0C to +85C Code = 0xFFFh, G = 1 Code = 0xFFFh, G = 1 Code = 0xFFFh, G = 1
VREF/C
DS21953A-page 2
(c) 2005 Microchip Technology Inc.
MCP4821/MCP4822
5V AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x, RL = 5 k to GND, CL = 100 pF, TA = -40 to +85C. Typical values at +25C. Parameters Output Amplifier Output Swing Phase Margin Slew Rate Short Circuit Current Settling Time Dynamic Performance DAC-to-DAC Crosstalk Major Code Transition Glitch Digital Feedthrough Analog Crosstalk Note 1: 2: By design, not production tested. Too small to quantify. -- -- -- -- <10 45 <10 <10 -- -- -- -- nV-s nV-s nV-s nV-s Note 2 1 LSb change around major carry (0111...1111 to 1000...0000) Note 2 Note 2 VOUT PM SR ISC tSETTLING -- -- -- -- -- 0.010 to VDD - 0.040 66 0.55 15 4.5 -- -- -- 24 -- V/s mA s Within 1/2 LSb of final value from 1/4 to 3/4 full-scale range Accuracy is better than 1 LSb for VOUT = 10 mV to (VDD - 40 mV) Sym Min Typ Max Units Conditions
3V AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 3V, AVSS = 0V, VREF = 2.048V external, output buffer gain (G) = 1x, RL = 5 k to GND, CL = 100 pF, TA = -40 to +85C. Typical values at 25C Parameters Power Requirements Input Voltage Input Current - MCP4821 Input Current - MCP4822 Hardware Shutdown Current Software Shutdown Current Power-On Reset threshold DC Accuracy Resolution INL Error DNL (Note 1) Offset Error Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Note 1: 2: n INL DNL VOS VOS/C gE 12 -12 -0.75 -1 -- -- -2 -- -- 3 0.3 0.02 0.5 -0.77 -0.15 -3 -- 12 0.75 1 -- -- 2 -- Bits LSb LSb % of FSR ppm/C ppm/C % of FSR ppm/C Device is monotonic Code 0x000h -45C to +25C +25C to +85C Code 0xFFFh, not including offset error VDD IDD ISHDN ISHDN_SW VPOR 2.7 -- -- -- -- -- -- 300 415 0.25 2 2.0 5.5 400 750 2 6 -- A A A V Digital inputs grounded, Output unloaded, code = 0x000 Sym Min Typ Max Units Conditions
G/C
By design, not production tested. Too small to quantify.
(c) 2005 Microchip Technology Inc.
DS21953A-page 3
MCP4821/MCP4822
3V AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 3V, AVSS = 0V, VREF = 2.048V external, output buffer gain (G) = 1x, RL = 5 k to GND, CL = 100 pF, TA = -40 to +85C. Typical values at 25C Parameters Internal Voltage Reference (VREF) Nominal Reference Voltage Temperature Coefficient (Note 1) VREF 2.008 -- -- -- -- Output Noise (VREF Noise) Output Noise Density ENREF (0.1-10 Hz) eNREF (1 kHz) eNREF (10 kHz) 1/f Corner Frequency Output Amplifier Output Swing Phase Margin Slew Rate Short Circuit Current Settling Time Dynamic Performance DAC-to-DAC Crosstalk Major Code Transition Glitch -- -- <10 45 -- -- nV-s nV-s Note 2 1 LSb change around major carry (0111...1111 to VOUT PM SR ISC tSETTLING -- -- -- -- -- 0.010 to VDD - 0.040 66 0.55 14 4.5 -- -- -- 24 -- V/s mA s Within 1/2 LSb of final value from 1/4 to 3/4 full-scale range Accuracy is better than 1 LSb for VOUT = 10 mV to (VDD - 40 mV) fCORNER -- -- -- -- 2.048 125 0.25 45 0.09 290 1.2 1.0 400 2.088 325 0.65 160 0.32 -- -- -- -- V ppm/C LSb/C ppm/C LSb/C Vp-p V/Hz V/Hz Hz VOUTA when G = 1x and Code = 0xFFFh -40C to 0C -40C to 0C 0C to +85C 0C to +85C Code = 0xFFFh, G = 1 Code = 0xFFFh, G = 1 Code = 0xFFFh, G = 1 Sym Min Typ Max Units Conditions
VREF/C
1000...0000)
Digital Feedthrough Analog Crosstalk Note 1: 2: By design, not production tested. Too small to quantify. -- -- <10 <10 -- -- nV-s nV-s Note 2 Note 2
5V EXTENDED TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x, RL = 5 k to GND, CL = 100 pF. Typical values at +125C by characterization or simulation. Parameters Power Requirements Input Voltage Input Current - MCP4821 Input Current - MCP4822 Hardware Shutdown Current Software Shutdown Current Power-On Reset threshold DC Accuracy Resolution INL Error Note 1: 2: n INL By design, not production tested. Too small to quantify. 12 -- -- 4 -- -- Bits LSb VDD IDD ISHDN ISHDN_SW VPOR 2.7 -- -- -- -- -- -- 350 440 1.5 5 1.85 5.5 -- -- -- -- A A A V Digital inputs grounded, Output unloaded, code = 0x000 Sym Min Typ Max Units Conditions
DS21953A-page 4
(c) 2005 Microchip Technology Inc.
MCP4821/MCP4822
5V EXTENDED TEMPERATURE SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x, RL = 5 k to GND, CL = 100 pF. Typical values at +125C by characterization or simulation. Parameters DNL (Note 1) Offset Error Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Internal Voltage Reference (VREF) Nominal Reference Voltage Temperature Coefficient (Note 1) VREF -- -- -- -- -- Output Noise (VREF Noise) Output Noise Density ENREF (0.1 - 10 Hz) eNREF (1 kHz) eNREF (10 kHz) 1/f Corner Frequency Output Amplifier Output Swing Phase Margin Slew Rate Short Circuit Current Settling Time Dynamic Performance DAC-to-DAC Crosstalk Major Code Transition Glitch -- -- <10 45 -- -- nV-s nV-s Note 2 1 LSb change around major carry (0111...1111 to VOUT PM SR ISC tSETTLING -- -- -- -- -- 0.010 to VDD - 0.040 66 0.55 17 4.5 -- -- -- -- -- V/s mA s Within 1/2 LSb of final value from 1/4 to 3/4 full-scale range Accuracy is better than 1 LSb for VOUT = 10 mV to (VDD - 40 mV) fCORNER -- -- -- -- 2.048 125 0.25 45 0.09 290 1.2 1.0 400 -- -- -- -- -- -- -- -- -- V ppm/C LSb/C ppm/C LSb/C Vp-p V/Hz V/Hz Hz VOUTA when G = 1x and Code = 0xFFFh -40C to 0C -40C to 0C 0C to +85C 0C to +85C Code = 0xFFFh, G = 1 Code = 0xFFFh, G = 1 Code = 0xFFFh, G = 1 Sym DNL VOS VOS/C gE Min -- -- -- -- -- Typ 0.25 0.02 -5 -0.10 -3 Max -- -- -- -- -- Units LSb % of FSR ppm/C % of FSR ppm/C Conditions Device is monotonic Code 0x000h +25C to +125C Code 0xFFFh, not including offset error
G/C
VREF/C
1000...0000)
Digital Feedthrough Analog Crosstalk Note 1: 2: By design, not production tested. Too small to quantify. -- -- <10 <10 -- -- nV-s nV-s Note 2 Note 2
(c) 2005 Microchip Technology Inc.
DS21953A-page 5
MCP4821/MCP4822
AC CHARACTERISTICS (SPITM TIMING SPECIFICATIONS)
Electrical Specifications: Unless otherwise indicated, VDD= 2.7V - 5.5V, TA= -40 to +125C. Typical values are at +25C. Parameters Schmitt Trigger High-Level Input Voltage (All digital input pins) Schmitt Trigger Low-Level Input Voltage (All digital input pins) Hysteresis of Schmitt Trigger Inputs Input Leakage Current Digital Pin Capacitance (All inputs/outputs) Clock Frequency Clock High Time Clock Low Time CS Fall to First Rising CLK Edge Data Input Setup Time Data Input Hold Time SCK Rise to CS Rise Hold Time CS High Time LDAC Pulse Width LDAC Setup Time SCK Idle Time before CS Fall Note 1: Sym VIH Min 0.7 VDD Typ -- Max -- Units V Conditions
VIL
--
--
0.2 VDD
V
VHYS ILEAKAGE CIN, COUT FCLK tHI tLO tCSSR tSU tHD tCHS tCSH tLD tLS tIDLE
-- -1 -- -- 15 15 40 15 10 15 15 100 40 40
0.05 VDD -- 10 -- -- -- -- -- -- -- -- -- -- --
-- 1 -- 20 -- -- -- -- -- -- -- -- -- -- A pF MHz ns ns ns ns ns ns ns ns ns ns SHDN = LDAC = CS = SDI = SCK + VREF = VDD or AVSS VDD = 5.0V, TA = +25C, fCLK = 1 MHz (Note 1) TA = +25C (Note 1) Note 1 Note 1 Applies only when CS falls with CLK high. (Note 1) Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
By design and characterization, not production tested.
tCSH CS tIDLE tCSSR Mode 1,1 SCK Mode 0,0 tSU SI MSb in LSb in tHD tHI tLO tCHS
LDAC tLS tLD
FIGURE 1-1:
SPITM Input Timing.
DS21953A-page 6
(c) 2005 Microchip Technology Inc.
MCP4821/MCP4822
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, AVSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-MSOP Note 1: JA JA JA -- -- -- 85 163 206 -- -- -- C/W C/W C/W TA TA TA -40 -40 -65 -- -- -- +125 +125 +150 C C C Note 1 Sym Min Typ Max Units Conditions
The MCP482X family of DACs operate over this extended temperature range, but with reduced performance. Operation in this range must not cause TJ to exceed the Maximum Junction Temperature of +150C.
(c) 2005 Microchip Technology Inc.
DS21953A-page 7
MCP4821/MCP4822
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
0.3 0.2 DNL (LSB) 5 4 3 2 1 0 -1 -2 -3 -4 -5 0 1024
Ambient Temperature
125C
85
25
0 -0.1 -0.2 -0.3 0 1024 2048 Code (Decimal) 3072 4096
INL (LSB)
0.1
2048 3072 Code (Decimal)
4096
FIGURE 2-1:
DNL vs. Code.
FIGURE 2-4: Temperature.
2.5 Absolute INL (LSB) 2 1.5 1 0.5 0
INL vs. Code and Ambient
0.2
0.1 DNL (LSB)
0
-0.1
-0.2 0 1024 2048 3072
125C 85C
4096
25C
-40
-20
0
20
40
60
80
100
120
Code (Decimal)
Ambient Temperature (C)
FIGURE 2-2: Temperature.
0.0766 Absolute DNL (LSB) 0.0764 0.0762 0.076 0.0758 0.0756 0.0754 0.0752 0.075 -40 -20 0
DNL vs. Code and Ambient
FIGURE 2-5: Temperature.
2 0 INL (LSB) -2 -4 -6
Absolute INL vs. Ambient
20
40
60
80
100 120
0
1024
2048 Code (Decimal)
3072
4096
Ambient Temperature (C)
FIGURE 2-3: Temperature.
Absolute DNL vs. Ambient
FIGURE 2-6:
Note:
INL vs. Code.
Single device graph for illustration of 64 code effect.
DS21953A-page 8
(c) 2005 Microchip Technology Inc.
MCP4821/MCP4822
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
2.050 2.049 2.048 2.047 2.046 2.045 2.044 2.043 2.042 2.041 2.040 -40 -20 0 20 40 60 80
Ambient Temperature (C)
VDD: 4V VDD: 3V VDD: 2.7V
Output Noise Voltage Density (V/ Hz)
100 1.E-04
Full Scale VOUT (V)
10 1.E-05
1 1.E-06
100 120
0.1 1.E-07 0.1 1E-1
1 1E+0
10 1E+1
100 1E+2
1k 1E+3
10k 1E+4
100k 1E+5
Frequency (Hz)
FIGURE 2-7: Full-Scale VOUTA w/G = 1 (VREF) vs. Ambient Temperature and VDD.
FIGURE 2-9: Output Noise Voltage Density (VREF Noise Density w/G = 1) vs. Frequency.
1.E-02 10.0 Output Noise Voltage (mV)
4.100 Full Scale VOUT (V) 4.096 4.092 4.088 4.084 4.080 4.076 -40 -20 0 20 40 60 80 100 120
Ambient Temperature (C)
VDD: 5.5V VDD: 5V
1.E-03 1.00
Eni (in VP-P)
0.10 1.E-04
Eni (in VRMS) Maximum Measurement Time = 10s
0.01 1.E-05 100 1E+2
1k 1E+3
10k 100k 1E+4 1E+5 Bandwidth (Hz)
1M 1E+6
FIGURE 2-8: Full-Scale VOUTA w/G = 2 (2VREF) vs.Ambient Temperature and VDD.
FIGURE 2-10: Output Noise Voltage (VREF Noise Voltage w/G = 1) vs. Bandwidth.
(c) 2005 Microchip Technology Inc.
DS21953A-page 9
MCP4821/MCP4822
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
340 320 300
5.5V 5.0V 4.0V 3.0V 2.7V VDD
600 550 500
5.5V 5.0V 4.0V 3.0V 2.7V VDD
IDD (A)
260 240 220 200 180 -40 -20 0 20 40 60 80 100 120
IDD (A)
280
450 400 350 300 -40 -20 0 20 40 60 80 100 120
Ambient Temperature (C)
Ambient Temperature (C)
FIGURE 2-11: MCP4821 IDD vs. Ambient Temperature and VDD.
20 18 16 14 12 10 8 6 4 2 0 265 270 275 280 285 290 295 300 305 310 315 320 >320
FIGURE 2-14: MCP4822 IDD vs. Ambient Temperature and VDD.
25 20 Occurrence 15 10 5 0 380 385 390 395 400 405 410 415 420 425 430 435 435 IDD (A) 440
Occurrence
IDD (A)
FIGURE 2-12: (VDD = 2.7V).
18 16 14 Occurrence 10 8 6 4 2 0 285 290 295 300 305
MCP4821 IDD Histogram
FIGURE 2-15: (VDD = 2.7V).
22 20 18 16 14 12 10 8 6 4 2 0 385 390 395 400
MCP4822 IDD Histogram
310
315
320
325
330
335
340
345
350
>350
Occurrence
12
405
410
415
420
425
IDD (A)
IDD (A)
FIGURE 2-13: (VDD = 5.0V).
MCP4821 IDD Histogram
FIGURE 2-16: (VDD = 5.0V).
MCP4822 IDD Histogram
DS21953A-page 10
(c) 2005 Microchip Technology Inc.
430
MCP4821/MCP4822
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
0.7 0.6 0.5
5.5V 5.0V 4.0V 3.0V 2.7V VDD
-0.05 -0.1 -0.15
VDD 5.5V 5.0V 4.0V 3.0V 2.7V
Gain Error (%)
ISHDN (A)
-0.2 -0.25 -0.3 -0.35 -0.4
0.4 0.3 0.2 0.1 0 -40 -20 0 20 40 60 80 100 120
-0.45 -0.5 -40 -20 0 20 40 60 80 100 120
Ambient Temperature (C)
Ambient Temperature (C)
FIGURE 2-17: Hardware Shutdown Current vs. Ambient Temperature and VDD.
4 3.5
5.5V 5.0V
FIGURE 2-20: Gain Error vs. Ambient Temperature and VDD.
4 3.5 3 2.5 2 1.5 1
3.0V 2.7V 4.0V VDD 5.5V 5.0V
ISHDN_SW (A)
3 2.5
4.0V
3.0V
2 1.5 1 -40 -20 0 20 40 60 80 100 120
2.7V VDD
VIN Hi Threshold (V)
-40
-20
0
20
40
60
80
100
120
Ambient Temperature (C)
Ambient Temperature (C)
FIGURE 2-18: Software Shutdown Current vs. Ambient Temperature and VDD.
0.11
FIGURE 2-21: VIN High Threshold vs. Ambient Temperature and VDD.
1.6
VDD 5.5V 5.0V
VIN Low Threshold (V)
Offset Error (%)
0.09 0.07 0.05
5.5V
1.5 1.4 1.3 1.2
0.03 0.01 -0.01 -0.03 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C)
VDD
4.0V
1.1 1 0.9 0.8 -40 -20 0 20 40 60 80 100 120
3.0V 2.7V
5.0V 4.0V 3.0V 2.7V
Ambient Temperature (C)
FIGURE 2-19: Offset Error vs. Ambient Temperature and VDD.
FIGURE 2-22: VIN Low Threshold vs. Ambient Temperature and VDD.
(c) 2005 Microchip Technology Inc.
DS21953A-page 11
MCP4821/MCP4822
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
2.5 2.25 16
VDD 5.5V 5.0V 4.0V 3.0V 2.7V
VIN_SPI Hysteresis (V)
1.75 1.5 1.25 1 0.75 0.5 0.25 0 -40 -20 0 20 40 60 80 100 120
IOUT_HI_SHORTED (mA)
2
15 14 13 12 11 10 -40 -20 0 20 40 60 80 100 120
5.5V 5.0V 4.0V 3.0V 2.7V VDD
Ambient Temperature (C)
Ambient Temperature (C)
FIGURE 2-23: Input Hysteresis vs. Ambient Temperature and VDD.
0.035 0.033
4.0V
FIGURE 2-26: IOUT High Short vs. Ambient Temperature and VDD.
6.0 5.0
VREF = 4.096V
VOUT_HI Limit (VDD-Y)(V)
0.031
VOUT (V)
0.029 0.027 0.025 0.023 0.021 0.019 0.017 0.015 -40 -20 0 20 40 60 80 100 120
3.0V 2.7V VDD
4.0 3.0 2.0 1.0 0.0 0
Output Shorted to VDD
Output Shorted to VSS
2
4
Ambient Temperature (C)
6 8 10 IOUT (mA)
12
14
16
FIGURE 2-24: VOUT High Limit vs. Ambient Temperature and VDD.
0.0028
VDD 5.5V 5.0V 4.0V 3.0V 2.7V
FIGURE 2-27:
IOUT vs. VOUT. Gain = 2.
VOUT_LOW Limit (Y-AVSS)(V)
0.0026 0.0024 0.0022 0.0020 0.0018 0.0016 0.0014 0.0012 0.0010 -40 -20 0 20 40 60 80 100 120
Ambient Temperature (C)
FIGURE 2-25: VOUT Low Limit vs. Ambient Temperature and VDD.
DS21953A-page 12
(c) 2005 Microchip Technology Inc.
MCP4821/MCP4822
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
VOUT VOUT SCK LDAC Time (1 s/div) LDAC Time (1 s/div)
FIGURE 2-28:
VOUT Rise Time 100%.
FIGURE 2-31:
VOUT Rise Time 25% - 75%.
VOUT VOUT SCK SCK LDAC Time (1 s/div) LDAC Time (1 s/div)
FIGURE 2-29:
VOUT Fall Time.
FIGURE 2-32: Shutdown.
VOUT Rise Time Exit
VOUT SCK
LDAC Time (1 s/div)
Ripple Rejection (dB)
Frequency (Hz)
FIGURE 2-30:
VOUT Rise Time 50%.
FIGURE 2-33:
PSRR vs. Frequency.
(c) 2005 Microchip Technology Inc.
DS21953A-page 13
MCP4821/MCP4822
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP4821 Pin No. 1 2 3 4 5 6 -- 7 8
PIN FUNCTION TABLE
MCP4822 Pin No. 1 2 3 4 5 -- 6 7 8 Symbol VDD CS SCK SDI LDAC SHDN VOUTB AVSS VOUTA Function Positive Power Supply Input (2.7V to 5.5V) Chip Select Input Serial Clock Input Serial Data Input Synchronization input used to transfer DAC settings from serial latches to output latches Hardware Shutdown Input DACB Output Analog Ground DACA Output
3.1
Positive Power Supply Input (VDD)
3.6
Hardware Shutdown Input (SHDN)
VDD is the positive power supply input. The input power supply is relative to AVSS and can range from 2.7V to 5.5V. A decoupling capacitor on VDD is recommended to achieve maximum performance.
SHDN is the hardware shutdown input that requires an active-low input signal to configure the DACs in their low-power Standby mode.
3.7 3.2 Chip Select (CS)
CS is the chip select input, which requires an active-low signal to enable serial clock and data functions.
DACx Outputs (VOUTA, VOUTB)
VOUTA and VOUTB are DAC outputs. The DAC output amplifier drives these pins with a range of AVSS to VDD.
3.8 3.3 Serial Clock Input (SCK)
SCK is the SPI compatible serial clock input.
Analog Ground (AVSS)
AVSS is the analog ground pin.
3.4
Serial Data Input (SDI)
SDI is the SPI compatible serial data input.
3.5
Latch DAC Input (LDAC)
LDAC (the latch DAC synchronization input) transfers the input latch registers to the DAC registers (output latches) when low. Can also be tied low if transfer on the rising edge of CS is desired.
DS21953A-page 14
(c) 2005 Microchip Technology Inc.
MCP4821/MCP4822
4.0 GENERAL OVERVIEW
INL < 0 111 110 101 Digital Input Code 100 011 010 001 000 INL < 0 DAC Output 1 LSb is the ideal voltage difference between two successive codes. Table 4-1 illustrates how to calculate LSb. Ideal Transfer Function Actual Transfer Function The MCP482X devices are voltage-output string DACs. These devices include rail-to-rail output amplifiers, internal voltage reference, shutdown and reset-management circuitry. Serial communication conforms to the SPI protocol. The MCP482X devices operate from 2.7V to 5.5V supplies. The coding of these devices is straight binary, with the ideal output voltage given by Equation 4-1, where G is the selected gain (1x or 2x), DN represents the digital input value and n represents the number of bits of resolution (n = 12).
EQUATION 4-1:
LSb SIZE
2.048V G D N VOUT = ------------------------------------n 2
FIGURE 4-1: 4.0.2
INL Accuracy.
DNL ACCURACY
TABLE 4-1:
Device MCP482X MCP482X
LSb SIZES
Gain 1x 2x LSb Size 2.048V/4096 4.096V/4096
DNL error is the measure of variations in code widths from the ideal code width. A DNL error of zero would imply that every code is exactly 1 LSb wide.
4.0.1
INL ACCURACY
111 110 101 Digital Input Code 100 011 010 001 000
INL error for these devices is the maximum deviation between an actual code transition point and its corresponding ideal transition point once offset and gain errors have been removed. These endpoints are from 0x000 to 0xFFF. Refer to Figure 4-1. Positive INL represents transition(s) later than ideal. Negative INL represents transition(s) earlier than ideal.
Actual Transfer Function
Ideal Transfer Function
Wide Code > 1 LSb Narrow Code < 1 LSb DAC Output
FIGURE 4-2: 4.0.3
DNL Accuracy.
OFFSET ERROR
Offset error is the deviation from zero voltage output when the digital input code is zero.
4.0.4
GAIN ERROR
Gain error is the deviation from the ideal output, VREF - 1 LSb, excluding the effects of offset error.
(c) 2005 Microchip Technology Inc.
DS21953A-page 15
MCP4821/MCP4822
4.1
4.1.1
Circuit Descriptions
OUTPUT AMPLIFIERS
Supply Voltages 5V VPOR VDD - VPOR Transient Duration
The DACs' outputs are buffered with a low-power, precision CMOS amplifier. This amplifier provides low offset voltage and low noise. The output stage enables the device to operate with output voltages close to the power supply rails. Refer to Section 1.0 "Electrical Characteristics" for range and load conditions. In addition to resistive load-driving capability, the amplifier will also drive high capacitive loads without oscillation. The amplifiers' strong outputs allow VOUT to be used as a programmable voltage reference in a system.
Time 10 Transient Duration (s) 8 6 4 2 0
Transients below the curve will NOT cause a reset
TA = +25C
4.1.1.1
Programmable Gain Block
The rail-to-rail output amplifier has configurable gain, allowing optimal full-scale outputs for differing voltage reference inputs. The output amplifier gain has two selections, a gain of 1 V/V (GA = 1) or a gain of 2 V/V (GA = 0). The output range is ideally 0.000V to 4095/4096 * 2.048V when G = 1, and 0.000 to 4095/4096 * 4.096V when G = 2. The default value for this bit is a gain of 2, yielding an ideal full-scale output of 0.000V to 4.096V due to the internal 2.048V VREF. Note that the near railto-rail CMOS output buffer's ability to approach AVSS and VDD establish practical range limitations. The output swing specification in Section 1.0 "Electrical Characteristics" defines the range for a given load condition.
Transients above the curve will cause a reset
1
2 3 4 VDD - VPOR (V)
5
FIGURE 4-3: 4.1.4
Typical Transient Response.
SHUTDOWN MODE
4.1.2
VOLTAGE REFERENCE
The MCP482X devices utilize internal 2.048V voltage reference. The voltage reference has low temperature coefficient and low noise characteristics. Refer to Section 1.0 "Electrical Characteristics" for the voltage reference specifications.
4.1.3
POWER-ON RESET CIRCUIT
The Power-On Reset (POR) circuit ensures that the DACs power-up with SHDN = 0 (high-impedance). The devices will continue to have a high-impedance output until a valid Write command is performed to either of the DAC registers and the LDAC pin meets the input low threshold. If the power supply voltage is less than the POR threshold (VPOR = 2.0V, typical), the DACs will be held in their reset state. They will remain in that state until VDD > VPOR and a subsequent Write command is received. Figure 4-3 shows a typical power supply transient pulse and the duration required to cause a reset to occur, as well as the relationship between the duration and trip voltage. A 0.1 F decoupling capacitor, mounted as close as possible to the VDD pin, provides additional transient immunity.
Shutdown mode can be entered by using either hardware or software commands. The hardware pin (SHDN) is only available on the MCP4821. During Shutdown mode, the supply current is isolated from most of the internal circuitry. The serial interface remains active, thus allowing a Write command to bring the device out of Shutdown mode. When the output amplifiers are shut down, the feedback resistance (typically 500 k) produces a high-impedance path to AVSS. The device will remain in Shutdown mode until the SHDN pin is brought high and a write command with SD = 1 is latched into the device. When a DAC is changed from Shutdown to Active mode, the output settling time takes < 10 s, but greater than the standard Active mode settling time (4.5 s).
DS21953A-page 16
(c) 2005 Microchip Technology Inc.
MCP4821/MCP4822
5.0
5.1
SERIAL INTERFACE
Overview
5.2
Write Command
The MCP482X family is designed to interface directly with the SPI port, available on many microcontrollers, and supports Mode 0,0 and Mode 1,1. Commands and data are sent to the device via the SDI pin, with data being clocked-in on the rising edge of SCK. The communications are unidirectional and, thus, data cannot be read out of the MCP482X devices. The CS pin must be held low for the duration of a write command. The write command consists of 16 bits and is used to configure the DAC's control and data latches. Register 5-1 details the input registers used to configure and load the DACA and DACB registers. Refer to Figure 1-1 and the AC Electrical Characteristics tables for detailed input and output timing specifications for both Mode 0,0 and Mode 1,1 operation.
The write command is initiated by driving the CS pin low, followed by clocking the four configuration bits and the 12 data bits into the SDI pin on the rising edge of SCK. The CS pin is then raised, causing the data to be latched into the selected DAC's input registers. The MCP482X devices utilize a double-buffered latch structure to allow both DACA's and DACB's outputs to be synchronized with the LDAC pin, if desired. Upon the LDAC pin achieving a low state, the values held in the DAC's input registers are transferred into the DACs' output registers. The outputs will transition to the value and held in the DACX register. All writes to the MCP482X devices are 16-bit words. Any clocks past 16 will be ignored. The most significant four bits are configuration bits. The remaining 12 bits are data bits. No data can be transferred into the device with CS high. This transfer will only occur if 16 clocks have been transferred into the device. If the rising edge of CS occurs prior, shifting of data into the input registers will be aborted.
REGISTER 5-1:
Upper Half: W-x A/B bit 15 W-x --
WRITE COMMAND REGISTER
W-x GA W-0 SHDN W-x D11 W-x D10 W-x D9 W-x D8 bit 8 Lower Half: W-x D7 bit 7
W-x D6
W-x D5
W-x D4
W-x D3
W-x D2
W-x D1
W-x D0 bit 0
bit 15
A/B: DACA or DACB Select bit 1 = Write to DACB 0 = Write to DACA -- Don't Care GA: Output Gain Select bit 1 = 1x (VOUT = VREF * D/4096) 0 = 2x (VOUT = 2 * VREF * D/4096) SHDN: Output Power-down Control bit 1 = Output Power-down Control bit 0 = Output buffer disabled, Output is high-impedance D11:D0: DAC Data bits 12-bit number "D" which sets the output value. Contains a value between 0 and 4095.
bit 14 bit 13
bit 12
bit 11-0
Legend R = Readable bit -n = Value at POR W = Writable bit 1 = bit is set U = Unimplemented bit, read as `0' 0 = bit is cleared x = bit is unknown
(c) 2005 Microchip Technology Inc.
DS21953A-page 17
MCP4821/MCP4822
CS 0 SCK config bits SDI A/B 12 data bits 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (Mode 1,1) (Mode 0,0)
-- GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LDAC
VOUT
FIGURE 5-1:
Write Command.
DS21953A-page 18
(c) 2005 Microchip Technology Inc.
MCP4821/MCP4822
6.0 TYPICAL APPLICATIONS
6.3 Output Noise Considerations
The MCP482X devices are general purpose DACs intended to be used in applications where a precision, low-power DAC with moderate bandwidth and internal voltage reference is required. Applications generally suited for the MCP482X devices include: * * * * * Set Point or Offset Trimming Sensor Calibration Precision Selectable Voltage Reference Portable Instrumentation (Battery-Powered) Calibration of Optical Communication Devices The voltage noise density (in V/Hz) is illustrated in Figure 2-9. This noise appears at VOUTX, and is primarily a result of the internal reference voltage. Its 1/f corner (fCORNER) is approximately 400 Hz. Figure 2-10 illustrates the voltage noise (in mVRMS or mVP-P). A small bypass capacitor on VOUTX is an effective method to produce a single-pole Low-Pass Filter (LPF) that will reduce this noise. For instance, a bypass capacitor sized to produce a 1 kHz LPF would result in an ENREF of about 100 VRMS. This would be necessary when trying to achieve the low DNL performance (at G = 1) that the MCP482X devices are capable of. The tested range for stability is .001F thru 4.7 F. VDD 0.1 F 0.1 F VDD CS1 VDD
6.1
Digital Interface
1 F VOUTB
VOUTA 1 F VOUTB
MCP482X
SDI
AVSS
SDO SCK LDAC CS0
6.2
Power Supply Considerations
The typical application will require a bypass capacitor in order to filter high-frequency noise. The noise can be induced onto the power supply's traces or as a result of changes on the DAC's output. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 6-1 illustrates an appropriate bypass strategy. In this example, the recommended bypass capacitor value is 0.1 F. This capacitor should be placed as close to the device power pin (VDD) as possible (within 4 mm). The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, AVDD and AVSS should reside on the analog plane.
AVSS
AVSS
FIGURE 6-1: Diagram.
Typical Connection
6.4
Layout Considerations
Inductively-coupled AC transients and digital switching noise can degrade the output signal integrity, potentially masking the MCP482X family's performance. Careful board layout will minimize these effects and increase the Signal-to-Noise Ratio (SNR). Bench testing has shown that a multi-layer board utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the MCP482X devices are capable of providing. Particularly harsh environments may require shielding of critical signals. Breadboards and wire-wrapped boards are not recommended if low noise is desired.
(c) 2005 Microchip Technology Inc.
DS21953A-page 19
PICmicro(R) Microcontroller
The MCP482X devices utilize a 3-wire synchronous serial protocol to transfer the DACs' setup and output values from the digital source. The serial protocol can be interfaced to SPITM or Microwire peripherals common on many microcontroller units (MCUs), including Microchip's PICmicro(R) MCUs and dsPIC(R) DSC family of MCUs. In addition to the three serial connections (CS, SCK and SDI), the LDAC signal synchronizes when the serial settings are latched into the DAC's output from the serial input latch. Figure 6-1 illustrates the required connections. Note that LDAC is active-low. If desired, this input can be tied low to reduce the required connections from 4 to 3. Write commands will be latched directly into the output latch when a valid 16 clock transmission has been received and CS has been raised.
MCP482X
VOUTA 0.1 F
SDI
MCP4821/MCP4822
6.5 Single-Supply Operation
6.5.1.1 Decreasing The Output Step Size
The MCP482X devices are Rail-to-Rail (R-R) input and output DACs designed to operate with a VDD range of 2.7V to 5.5V. Its output amplifier is robust enough to drive common, small-signal loads directly, thus eliminating the cost and size of an external buffer for most applications. If the application is calibrating the threshold of a diode, transistor or resistor tied to AVSS, a threshold range of 0.8V may be desired to provide 200 V resolution. Two common methods to achieve a 0.8V range is to either reduce VREF to 0.82V (would require MCP492X device and external voltage reference) or use a voltage divider on the DAC's output. Typically, when using a lowvoltage VREF, the noise floor causes SNR error that is intolerable. The voltage divider method provides some advantages when VREF needs to be very low or when the desired output voltage is not available. Using two resistors to scale the output range down to the precise desired level is a simple, low-cost method to achieve very small step sizes. Example 6-1 illustrates this concept. Note that the bypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noise of the DAC and the induced noise from the environment. The MCP482X family's low 0.75 (max.) DNL performance is critical to meeting calibration accuracy in production.
6.5.1
DC SET POINT OR CALIBRATION
A common application for a DAC with the MCP482X family's performance is a digitally-controlled set point and/or calibration of variable parameters, such as sensor offset or slope. 12-bit resolution provides 4096 output steps. If G = 1 is selected, then the internal 2.048 VREF would produce 500 V of resolution. If G = 2 is selected, the internal 2.048 VREF would produce 1 mV of resolution.
VDD
RSENSE VDD VOUT R1
VCC+
Comparator VTRIP VCC-
MCP482X
R2 SPITM 3 D V OUT = 2.048 G -------12 2 R2 V trip = VOUT -------------------- R 1 + R 2
0.1 uF
G = Gain select (1x or 2x) D = Digital value of DAC (0 - 4096)
EXAMPLE 6-1:
Set Point or Threshold Calibration.
DS21953A-page 20
(c) 2005 Microchip Technology Inc.
MCP4821/MCP4822
6.5.1.2 Building a "Window" DAC
When calibrating a set point or threshold of a sensor, rarely does the sensor utilize the entire output range of the DAC. If the LSb size is adequate to meet the application's accuracy needs, the resolution is sacrificed without consequences. If greater accuracy is needed, then the output range will need to be reduced to increase the resolution around the desired threshold. If the threshold is not near VREF, 2VREF or AVSS, then creating a "window" around the threshold has several advantages. One simple method to create this "window" is to use a voltage divider network with a pullup and pull-down resistor. Example 6-2 and Example 6-4 illustrates this concept. The MCP482X family's low 0.75 (max.) DNL performance is critical to meet calibration accuracy in production.
VCC+ VDD VOUT R3 R1
RSENSE
VCC+
Comparator VTRIP 0.1 F VCCVCC-
MCP482X
R2 SPITM 3
D V OUT = 2.048 G ------12 2 R2R3 R 23 = -----------------R2 + R 3 V 23 ( V CC+ R 2 ) + ( VCC- R 3 ) = ----------------------------------------------------R 2 + R3
G = Gain select (1x or 2x) D = Digital value of DAC (0 - 4096) R1 VOUT VO R23 V23
Thevenin Equivalent
V OUT R23 + V 23 R 1 V trip = ------------------------------------------R 2 + R 23
EXAMPLE 6-2:
Single-Supply "Window" DAC.
(c) 2005 Microchip Technology Inc.
DS21953A-page 21
MCP4821/MCP4822
6.6 Bipolar Operation
Bipolar operation is achievable using the MCP482X devices by using an external operational amplifier (op amp). This configuration is desirable due to the wide variety and availability of op amps. This allows a general purpose DAC, with its cost and availability advantages, to meet almost any desired output voltage range, power and noise performance. Example 6-3 illustrates a simple bipolar voltage source configuration. R1 and R2 allow the gain to be selected, while R3 and R4 shift the DAC's output to a selected offset. Note that R4 can be tied to VDD, instead of AVSS, if a higher offset is desired. Note that a pull-up to VDD could be used, instead of R4 or in addition to R4, if a higher offset is desired.
R2 VDD VDD VOUT MCP482X R4 SPITM 3 D V OUT = 2.048 G ------12 2 V OUT R4 VIN+ = ------------------R3 + R 4 R2 R2 VO = V IN+ 1 + ----- - V DD ----- R 1 R1 R3 R1 VIN+ VCC- 0.1 F VCC+ VO
G = Gain select (1x or 2x) D = Digital value of DAC (0 - 4096)
EXAMPLE 6-3: 6.6.1
Digitally-Controlled Bipolar Voltage Source.
4. Next, solve for R3 and R4 by setting the DAC to 4096, knowing that the output needs to be +2.05V. R4 2.05V + ( 0.5 4.096V ) 2 ---------------------- = ------------------------------------------------------ = -( R 3 + R4 ) 1.5 4.096V 3 If R4 = 20 k, then R3 = 10 k
DESIGN A BIPOLAR DAC USING EXAMPLE 6-3
An output step magnitude of 1 mV, with an output range of 2.05V, is desired for a particular application. 1. 2. Calculate the range: +2.05V - (-2.05V) = 4.1V. Calculate the resolution needed: 4.1V/1 mV = 4100 Since 212 = 4096, 12-bit resolution is desired. 3. The amplifier gain (R2/R1), multiplied by fullscale VOUT (4.096V), must be equal to the desired minimum output to achieve bipolar operation. Since any gain can be realized by choosing resistor values (R1+R2), the VREF value must be selected first. If a VREF of 4.096V is used (G=2), solve for the amplifier's gain by setting the DAC to 0, knowing that the output needs to be -2.05V. The equation can be simplified to: -R2 - 2.05 -------- = ---------------R1 4.096V R2 1 ----- = -2 R1
If R1 = 20 k and R2 = 10 k, the gain will be 0.5
DS21953A-page 22
(c) 2005 Microchip Technology Inc.
MCP4821/MCP4822
6.7 Selectable Gain and Offset Bipolar Voltage Output Using A Dual DAC
This circuit is typically used for linearizing a sensor whose slope and offset varies. The equation to design a bipolar "window" DAC would be utilized if R3, R4 and R5 are populated.
In some applications, precision digital control of the output range is desirable. Example 6-4 illustrates how to use the MCP482X family to achieve this in a bipolar or single-supply application.
R2 VDD VOUTA MCP482X VDD DACA (Gain Adjust) VOUTB MCP482X SPITM 3 VCC- DB V OUTB = ( 2.048V G B ) ------12 2 VOUTB R 4 + VCC- R3 VIN+ = ----------------------------------------------R3 + R 4 R2 R2 V O = V IN+ 1 + ----- - VOUTA ----- R 1 R1 Offset Adjust Gain Adjust DA V OUTA = ( 2.048V G A ) ------12 2 AVSS = GND G = Gain select (1x or 2x) D = Digital value of DAC (0 - 4096) DACB (Offset Adjust) R4 R3 VCC+ R5 VO R1
VCC+
0.1 F
VCC-
Bipolar "Window" DAC using R4 and R5 Thevenin Equivalent V CC+ R 4 + VCC- R5 V45 = ------------------------------------------R 4 + R5 V OUTB R45 + V 45 R 3 V IN+ = ---------------------------------------------R 3 + R 45 R4 R5 R 45 = -----------------R4 + R5 R2 R2 V O = VIN+ 1 + ----- - V OUTA ----- R 1 R1 Offset Adjust Gain Adjust
EXAMPLE 6-4:
Bipolar Voltage Source with Selectable Gain and Offset.
(c) 2005 Microchip Technology Inc.
DS21953A-page 23
MCP4821/MCP4822
6.8 Designing A Double-Precision DAC Using A Dual DAC
1. Calculate the resolution needed: 4.1V/1 V = 4.1e06. Since 222 = 4.2e06, 22-bit resolution is desired. Since DNL = 0.75 LSb, this design can be attempted with the MCP482X family. Since DACB`s VOUTB has a resolution of 1 mV, its output only needs to be "pulled" 1/1000 to meet the 1 V target. Dividing VOUTA by 1000 would allow the application to compensate for DACB`s DNL error. If R2 is 100, then R1 needs to be 100 k. The resulting transfer function is shown in the equation of Example 6-5.
Example 6-5 illustrates how to design a single-supply voltage output capable of up to 24-bit resolution from a dual 12-bit DAC. This design is simply a voltage divider with a buffered output. As an example, if a similar application to the one developed in Section 6.6.1 "Design a Bipolar DAC Using Example 6-3" required a resolution of 1 V instead of 1 mV, and a range of 0V to 4.1V, then 12-bit resolution would not be adequate.
2.
3. 4.
VDD DACA (Fine Adjust) VOUTA R1 >> R2 VOUTB R2 0.1 F DACB (Course Adjust) SPITM 3 DA V OUTA = 2.048V G A ------12 2 V OUTA R2 + V OUTB R1 VO = ----------------------------------------------------R1 + R 2 DB VOUTB = 2.048V G B ------12 2
VCC+ VO R1
MCP482X VDD
MCP482X
VCC-
G = Gain select (1x or 2x) D = Digital value of DAC (0 - 4096)
EXAMPLE 6-5:
Simple, Double-Precision DAC.
DS21953A-page 24
(c) 2005 Microchip Technology Inc.
MCP4821/MCP4822
6.9 Building A Programmable Current Source
Example 6-6 illustrates a variation on a voltage follower design where a sense resistor is used to convert the DAC's voltage output into a digitally-selectable current source. Adding the resistor network from Example 6-2 would be advantageous in this application. The smaller RSENSE is, the less power dissipated across it. However, this also reduces the resolution that the current can be controlled with. The voltage divider, or "window", DAC configuration would allow the range to be reduced, thus increasing resolution around the range of interest. When working with very small sensor voltages, plan on eliminating the amplifier's offset error by storing the DAC's setting under known sensor conditions. VDD VOUT VCC+ Load IL VCC- Ib 3 Rsense D V OUT = 2.048V G ------12 2 IL I b = --- V OUT I L = -------------- x ----------Rsense + 1 G = Gain select (1x or 2x) D = Digital value of DAC (0 - 4096)
MCP482X
SPITM
EXAMPLE 6-6:
Digitally-Controlled Current Source.
(c) 2005 Microchip Technology Inc.
DS21953A-page 25
MCP4821/MCP4822
7.0
7.1
DEVELOPMENT SUPPORT
Evaluation & Demonstration Boards 7.2 Application Notes
The Mixed Signal PICtailTM Demo Board supports the MCP482X family of devices. Refer to www.microchip.com for further information on this product's capabilities and availability.
Application notes illustrating the performance and implementation of the MCP482X family are planned but are currently not released. Refer to www.microchip.com for further information.
DS21953A-page 26
(c) 2005 Microchip Technology Inc.
MCP4821/MCP4822
8.0
8.1
PACKAGING INFORMATION
Package Marking Information
8-Lead MSOP XXXXXX YWWNNN Example: 4821E 524256
8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW
Example: MCP4821 E/P e3 256 ^ 0524
8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN
Example: MCP4821E e3 SN^^ 0524 256
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2005 Microchip Technology Inc.
DS21953A-page 27
MCP4821/MCP4822
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E E1
p D 2 B n 1
A c A1 (F)
A2
L
8 Number of Pins .026 BSC Pitch A .043 Overall Height A2 .030 .033 .037 Molded Package Thickness .006 .000 A1 Standoff E .193 TYP. Overall Width E1 .118 BSC Molded Package Width .118 BSC D Overall Length L .016 .024 .031 Foot Length Footprint (Reference) F .037 REF Foot Angle 0 8 c Lead Thickness .003 .006 .009 .009 .012 .016 Lead Width B 5 Mold Draft Angle Top 5 15 5 5 15 Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
Units Dimension Limits n p
MIN
INCHES NOM
MAX
MIN
MILLIMETERS* NOM 8 0.65 BSC 0.75 0.85 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.95 REF 0 0.08 0.22 5 5 -
MAX
1.10 0.95 0.15
0.80 8 0.23 0.40 15 15
JEDEC Equivalent: MO-187
Drawing No. C04-111
DS21953A-page 28
(c) 2005 Microchip Technology Inc.
MCP4821/MCP4822
8-Lead Plastic Dual In-line (P) - 300 mil (PDIP)
E1
D 2 n 1 E
A
A2
c
L A1
eB
B1 p B
Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB
MIN
INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10
MAX
MIN
.140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5
.170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15
MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MAX
4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018
(c) 2005 Microchip Technology Inc.
DS21953A-page 29
MCP4821/MCP4822
8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC)
E E1
p
D 2 B n 1
h 45
c A A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D h L c B
MIN
.053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0
INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12
MAX
MIN
.069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15
MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12
MAX
1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057
DS21953A-page 30
(c) 2005 Microchip Technology Inc.
MCP4821/4822
APPENDIX A: REVISION HISTORY
Revision A (June 2005)
* Original Release of this Document.
(c) 2005 Microchip Technology Inc.
DS21953A-page 31
MCP4821/4822
NOTES:
DS21953A-page 32
(c) 2005 Microchip Technology Inc.
MCP4821/4822
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package Examples:
a) MCP4821T-E/SN: Tape and Reel Extended Temperature, 8LD SOIC package. MCP4821T-E/MS: Tape and Reel Extended Temperature, 8LD MSOP package. MCP4821-E/SN: Extended Temperature, 8LD SOIC package. MCP4821-E/MS: Extended Temperature, 8LD MSOP package. MCP4821-E/P: Extended Temperature, 8LD PDIP package. MCP4822T-E/SN: Tape and Reel Extended Temperature, 8LD SOIC package. MCP4822-E/P: Extended Temperature, 8LD PDIP package. MCP4822-E/SN: Extended Temperature, 8LD SOIC package.
b) Device: MCP4821: MCP4821T: MCP4822: MCP4822T: 12-Bit DAC with SPITM Interface 12-Bit DAC with SPI Interface (Tape and Reel) (SOIC, MSOP) 12-Bit DAC with SPI Interface 12-Bit DAC with SPI Interface (Tape and Reel) (SOIC, MSOP)
c) d) e)
Temperature Range:
E
= -40C to +125C
a)
Package:
MS = Plastic MSOP, 8-lead P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC, (150 mil Body), 8-lead
b) c)
(c) 2005 Microchip Technology Inc.
DS21953A-page 33
MCP4821/4822
NOTES:
DS21953A-page 34
(c) 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2005 Microchip Technology Inc.
DS21953A-page 35
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
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04/20/05
DS21953A-page 36
(c) 2005 Microchip Technology Inc.

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